ASIC and Logic Design Engineering Manager (Teradyne, North Reading)

Teradyne · North Reading, MA, US

Logic Design Manager leading a team of 4-6 engineers in designing and verifying FPGAs for next-generation test products, with responsibility for multiple simultaneous projects and engineering team management.

Requirements

Experience: 12+ years

Education: BACHELOR

Required

AXI4CDCClearcaseDDR3+Ethernet-based protocolsFPGA simulation and testingFPGA/ASIC project leadGitIntel/Altera FPGAsJIRALINTPCIQuartusRTL codingSerDesSoftware SimulationSPIStatic timing analysis (STA)VerilogVivado

Preferred

ARM based MCUsCC++DACDigital verification tools and methodologiesFirst level manager of an engineering teamMicroprocessor designMS Projectsignal processingTest Automation Infrastructure DesignVSM

ASIC and Logic Design Engineering Manager (Teradyne, North Reading)

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