ASIC/FPGA Design Verification Engineer (Teradyne, N. Reading, MA)

Teradyne · North Reading, MA, US

Digital Logic Verification Engineer with FPGA design expertise responsible for FPGA verification, testbench development, and System Verilog/UVM test creation within Teradyne's Logic Design Engineering team.

Requirements

Experience: 3+ years

Required

Digital Logic VerificationSystem VerilogUVM MethodologyVerilogXilinx Vivado

Preferred

AXI ProtocolCI/CDDDR ProtocolEmbedded firmware designSPI protocolSystem Verilog Assertions

ASIC/FPGA Design Verification Engineer (Teradyne, N. Reading, MA)

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