ASIC/FPGA Design Verification Engineer (Teradyne, N. Reading, MA)

Teradyne · North Reading, MA, US

Digital Logic Verification Engineer role focused on FPGA verification, working with cross-functional teams to deliver high-quality, robust designs at Teradyne's North Reading, MA development center.

Requirements

Experience: 5+ years

Required

CI/CDDigital Logic VerificationIP protocols (SPI, AXI, DDR)System VerilogSystem Verilog assertion-based verification methodologiesUVM MethodologyVerilogXilinx Vivado

Preferred

Embedded firmware design

ASIC/FPGA Design Verification Engineer (Teradyne, N. Reading, MA)

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