Senior FPGA Design Engineer (Nextest, San Jose, CA)

Teradyne · San Jose, CA, US

FPGA Design Engineer supporting the development of cutting-edge memory test solutions for Flash and DRAM test instrumentation at Teradyne's Memory Test Division.

Requirements

Experience: 3+ years

Education: BACHELOR

Required

CC++Design & Architectural patternsDigital simulation testbench creationLaboratory validationRTL codingStatic timing analysis (STA)SynthesisTiming closureVerilog

Preferred

Altera/AMD FPGA tool flowsFPGA Transceiver based designLinuxMemory interfaces (DDR, SDRAM, Flash)OscilloscopeScientific or industrial instrumentationScriptingSensorsSignal generatorsUVM MethodologyWindows

Senior FPGA Design Engineer (Nextest, San Jose, CA)

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