Advanced ASIC Physical Design Lead (Teradyne, North Reading, MA)

Teradyne · North Reading, MA, US

Physical Design Lead for advanced-node ASIC development within Teradyne's Digital ASIC Group. Will lead physical design engineers through RTL-to-GDSII execution for complex mixed-signal ASICs and mentor team members.

Requirements

Experience: 10+ years

Education: BACHELOR

Required

Advanced process nodes (5nm, 3nm)Cadence EDA toolsConstraint DevelopmentDDR5LeadershipMakeMicroprocessor designPCIPythonRTL-to-GDSII flowsSerDesSignoff methodologiesStatic timing analysis (STA)TCLUFS

Preferred

Clock domain crossing checks (CDC)DRC/LVS signoffEM/IR analysisLogical equivalence checking (LEC)Place-and-route (P&R)Synthesis

Advanced ASIC Physical Design Lead (Teradyne, North Reading, MA)

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